As the need increases for memory devices that are both smaller and have larger data capacities, advancements in stacked IC packaging techniques have been developed to facilitate this need. Stacked IC packaging generally involves stacking multiple integrated circuit dies onto a substrate within a single IC package.
One stacked IC packaging approach involves stacking the IC dies in a “pyramid” stacking arrangement in which a smaller die is stacked on a larger die, with both dies wire bonded to the substrate. The use of wire bonding necessarily requires that access to bonding pads of each of the dies be available; consequently, the upper die, when stacked on the lower die, must be small so as to not inhibit access to the bonding pads of the lower die. The “pyramid” stacking arrangement has, for example, been used with same function dies (e.g., two Flash memory dies) or different function dies (e.g., one Flash memory die and one SRAM die). Stacking of two or three dies has been done for stacked Chip Scale Packages (stacked CSP) and stacked Thin Small Outline Packages (TSOP). A disadvantage of the “pyramid” stacking arrangement is that the dies must be different sizes, which presents a problem in memory device applications where several like-sized memory dies are used.
Another conventional IC packaging approach that facilitates stacking like-sized dies involves placing a spacer (e.g., a relatively thick insulator) between the dies. Although the spacer provides sufficient space between the dies so that wire bonded to the lower die is made possible, the spacer disadvantageously either makes the IC package thicker, or limits the number of dies that can fit within the IC package of a predetermined thickness.
FIG. 19 is a simplified cross-sectional side view showing an electronic device 200 produced in accordance with a stacked IC packaging technique that is disclosed in Published U.S. Application No. 20070218588. Device 200 includes IC dies 212 to 218 disposed in a “staircase” stacking arrangement on a substrate 201, and are respectively connected to a finger pad 203 by way of wire bonds 222 to 228. Adhesive layers 232 to 238 are disposed under each IC die 212 to 218. A molded plastic housing 240 is formed over substrate 201, dies 212 to 218 and wire bonds 222 to 228.
The “staircase” stacking arrangement of device 200 avoids the problems of the spacer approach (discussed above) by exposing bond pads on each IC die without requiring a thick spacer between the dies. However, device 200 has several problems associated with the formation of wire bonds 222 to 228 between each IC die 212 to 218 and substrate 201. First, by forming wire bonds to each IC die, the number of IC die that can be stacked in the “staircase” stacking arrangement of device 200 is limited due to the increasing length of the wire bonds to the uppermost IC die (e.g., wire bonds 228). Further, because each IC die 212 to 218 is connected at its lower end to finger pad 203, the size of finger pad 203 must be made large to accommodate a potentially large number of wire bonds (thereby wasting substrate surface area in applications where a smaller number of die are used). Moreover, the longer wire bonds (e.g., wire bonds 226 and 228) are subject to greater parasitic inductances than shorter wire bonds, and the overlapping wire arrangement increases the risk that longer wire bonds may sag and short against the underlying shorter wire bonds. Additionally, as understood by those in the art, longer wire bonds are more prone to the wire sweep problem during molding process that can cause electrical open defects. Finally, the overlapping wire bond arrangement makes repair and reworking of a damaged or misplaced wire bond difficult without removing the wire bonds disposed over or adjacent to the damaged/misplaced wire bond.
FIG. 20 is a simplified cross-sectional side view showing an electronic device 300 produced in accordance with a “staggered” stacking arrangement, also disclosed in Published U.S. Application No. 20070218588, in which IC dies 312 to 318 disposed in an offset “staggered” arrangement on a substrate 301 such that every other die is connected to one of a first finger pad 303 or a second finger pad 305 by way of wire bonds 322 to 328. This approach reduces the length of the wire bonds extending to the uppermost IC die and may somewhat simplify repair/rework, but still has many of the problems discussed above with reference to the “staircase” stacking arrangement (e.g., the size of finger pads 303 and 205 must be made large, the wire bonds are subject to parasitic inductances, the overlapping wire arrangement increases the risk of sagging and shorting, and is subject to the wire sweep problem).
FIG. 21 is a simplified cross-sectional side view showing an electronic device 400 produced in accordance with another “staircase” stacking arrangement that is also disclosed in Published U.S. Application No. 20070218588. Similar to device 200 (discussed above), bonding wire 432 is connected between a finger pad 403 and a lowermost IC die 412. Device 400 differs from device 200 in that, instead of having each wire bond extend from the substrate to its associated IC die, subsequent bonding wires 424 to 428 of device 400 are connected between adjacent IC die (i.e., bonding wire 424 is connected between die 412 and die 414, bonding wire 426 is connected between die 414 and die 416, and bonding wire 428 is connected between die 416 and die 418). This wiring arrangement is utilized in, e.g., memory applications where “shared” (e.g., addressing and data) signals are transmitted to all of the memory dies. However, this arrangement has a problem in that it does not provide for dedicated (unshared) (e.g., Chip Select and Chip Enable) signals that are unique to each of the memory die. That is, the only way to send dedicated signals to each of IC die 412 to 418, based on the teachings of Published U.S. Application No. 20070218588, is to provide separate wire bonds extending from substrate 401 to each of IC dies 412 to 418 (i.e., similar to wire bonds 222 to 228, described above with reference to FIG. 2), which would be subject to the same problems as those described above with reference to FIG. 2.
FIG. 22 is a simplified cross-sectional side view showing an electronic device 500 produced in accordance with yet another stacking arrangement that is also disclosed in Published U.S. Application No. 20070218588. Similar to device 400 (discussed above), IC dies 512 to 518 are arranged in “staircase” stacking arrangement on substrate 501, and bonding wires 522 to 528 are connected between finger pad 503 and IC die 512, and between IC dies 514 to 518 in the manner that supports “shared” signals. In addition, another (e.g., a memory control) IC die 519 is mounted on IC die 518, and wire bonds 529 are connected between corresponding finger pad 505 and IC die 519 in order to support dedicated signals transmitted to and from IC die 519. This arrangement has problems similar to those discussed above with reference to FIG. 4, and in addition re-introduces the problems discussed above with reference to FIG. 2 regarding longer wire bonds.
What is needed is a method for producing electronic devices including stacked IC (e.g., memory or logic) dies that avoids the problems associated with the conventional stacking arrangements set forth above.